1. Field of the Invention
This invention relates to a method of manufacture of a semiconductor device.
Priority is claimed on Japanese Patent Application No. 2004-325070, filed Nov. 9, 2004, the content of which is incorporated herein by reference.
2. Description of Related Art
LSI devices and other integrated circuits have been mounted in portable telephone sets, notebook-type personal computers, PDAs (Personal Digital Assistants), and other electronic equipment, in efforts to make electronic equipment more compact and provide sophisticated functions. Such LSI devices and other integrated circuits contain field effect transistors (MOSFETs), capacitors, resistors and similar, integrated and stacked on a semiconductor substrate.
However, trends toward greater compactness of electronic equipment in recent years have led to increased demands for smaller device components, and it has become increasingly necessary to reduce the film thickness of gate oxide films in MOSFETs. In light of such circumstances, it is anticipated that reduced gate oxide film thicknesses will give rise to problems of degradation of the reliability of the gate oxide film (TDDB degradation, increased leakage currents, reduced withstand voltages, and similar) in such processes as impurity doping using the gate electrode as a mask and plasma damage during gate electrode processing, and ion implantation into channel regions, source regions, and drain regions.
As one solution to such problems, a MOSFET formation method using a dummy gate pattern has been proposed (see for example Japanese Unexamined Patent Application, First Publication No. 2004-241751). This dummy gate pattern formation method is described briefly as follows. First, a dummy insulating film, which is a thin silicon oxide film, is formed on the silicon substrate surface. Next, a polysilicon film for use as a dummy gate pattern is formed on the dummy insulating film. Then, photolithography and etching are used to pattern the polysilicon film in the shape of the dummy gate pattern. Next, the dummy gate pattern is used as a mask to perform ion implantation of the silicon substrate with the dummy insulating film intervening, forming a channel region and source and drain regions. Then, the dummy gate pattern and pad oxide film are removed, and a trench portion is formed. A buried gate insulating film and gate electrode are formed in this trench portion.
In this method, after ion implantation using the dummy gate pattern as a mask, the dummy gate pattern and dummy insulating film are removed, and then a new gate insulating film and gate electrode are formed. By this means, plasma damage during gate electrode shaping, damage upon ion implantation into the channel region and source and drain regions, and other data to the newly formed gate insulating film and gate electrode can be avoided.
However, in the method disclosed in the above patent document, a plurality of processes, including formation of a dummy gate pattern oxide film, deposition of a polysilicon film, patterning of the polysilicon film, etching, and formation of a dummy gate pattern, are necessary in order to form the dummy gate pattern. Further, the polysilicon used as the material of the dummy gate pattern is generally expensive. Also, processing at high temperatures is required in order to pattern the polysilicon to the prescribed shape, so that large amounts of energy are necessary.
In addition, despite the fact that the dummy gate pattern requires these numerous processes, entails high costs, and requires large amounts of energy, the dummy insulating film and dummy gate pattern formed on the silicon substrate in the above disclosed patent document are removed from the substrate after ion implantation.
Hence in the case of a pattern which is ultimately removed, there is thought to be an urgent need for proposals of a method of formation of a dummy gate pattern which can be formed at low cost, and which can withstand the elevated temperature and other conditions of ion implantation processes even when formed at low cost.